spice device model si4946ey vishay siliconix this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number for guaranteed specification limits. document number: 71564 www.vishay.com 05-nov-99 1 dual n-channel 50-v (d-s) dual mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model describes the typical electrical characteristics of the n-channel vertical dmos. the subcircuit model schematic is extracted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0-to-5v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c g d model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. subcircuit model schematic
spice device model si4649ey vishay siliconix www.vishay.com document number: 71564 2 05-nov-99 specifications (t j = 25 c unless otherwise noted) parameter symbol test condition measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.75 v on-state drain current a i d(on) v ds = 5 v, v gs = 10 v 100 a v gs = 10v, i d = 4.5 a 0.048 drain-source on-state resistance a r ds(on) v gs = 4.5v, i d = 3.9 a 0.058 ? forward transconductance a g fs v ds = 15 v, i d = 4.5 a 13 s diode forward voltage a v sd i s = 2 a, v gs = 0 v 0.81 v dynamic b total gate charge b q g 16 gate-source charge b q gs 4 gate-drain charge b q gd v ds = 30 v, v gs = 10 v, i d = 4.5 a 3 nc turn-on delay time b t d(on) 10 rise time b t r 12 turn-off delay time b t d(off) 22 fall time b t f v dd = 30 v, r l = 30 ? i d ? 1 a, v gen = 10 v, r g = 6 ? 28 source-drain reverse recovery time t rr i f = 2 a, di/dt = 100 a/ s 35 ns notes a. for design aid only; not subject to production testing. b. pulse test; pulse width 300 s, duty cycle 2%.
spice device model si4946ey vishay siliconix document number: 71564 www.vishay.com 05-nov-99 3 comparison of model with measured data (t j =25 c unless otherwise noted)
|
